(a) Field of the Invention
The present invention relates to a flash memory and a fabrication method thereof, and more particularly to a flash memory where a tunneling oxide and a floating gate are formed only in a portion in which electrons are injected.
(b) Description of the Related Art
In general, a flash memory, which is a memory device designed to realize merits of EPROM (erasable programmable read only memory) and EEPROM (electrically erasable programmable read only memory) simultaneously, aims at electrical programming and erasure of data and low production cost in aspects of simplicity of fabrication processes, small-sizing of chips, etc.
In addition, although the flash memory is a nonvolatile semiconductor memory where data are not erased even when a power turns off, since it has the property of ROM (random access memory) in that programming and erasure of information is easily achieved in a system, it has been used for a memory device substituting a memory card or a hard disk of an office automation equipment.
The programming of data in the flash memory is achieved by injection of hot electrons. In other words, when hot electrons are generated in a channel by a potential difference between a source and a drain, some of the hot electrons, which obtain more than 3.1 eV, which is a potential barrier between a polycrystalline silicon layer constituting a gate and an oxide film, move to and are stored in a floating gate by a high electric field applied across a control gate.
Therefore, the flash memory is designed such that the hot electrons are generated, although a general MOS device is designed such that generation of the hot electrons is suppressed because they are the cause of deterioration of the device.
Conventional techniques for the flash memory are disclosed in U.P. Pat. Nos. 6,579,761, 6,512,262, 6,501,125, 6,261,905, 6,153,494, and 6,069,382.
Hereinafter, a conventional flash memory will be in brief described with reference to FIGS. 1a to 2.
FIGS. 1a and 1b are sectional views showing a conventional method for fabricating the flash memory, and FIG. 2 is a top view of the conventional flash memory shown in FIG. 1b. 
First, as shown in FIG. 1a, a tunneling oxide 2 is formed at a thickness of an order of 100 Å on a semiconductor substrate 1, a floating gate 3 made of polycrystalline silicon is formed at a thickness of an order of 2,500 Å on the tunneling oxide 2, and then a gate insulation film 4 having an oxide/nitride/oxide (ONO; hereinafter referred to as “ONO”) structure is formed on the floating gate 3.
In order to form the gate insulation film 4 having the ONO structure, a lower oxide film is formed on the floating gate 3 by thermally oxidizing a polycrystalline silicon layer of the floating gate 3, a silicon nitride film is formed on the lower oxide film by using a thermal process, and then an upper oxide film is formed on the silicon nitride film by using a thermal process and is annealed.
Subsequently, a control gate 5 to function as an actual electrode is formed by depositing a polycrystalline silicon layer at a thickness of an order of 2,500 Å on the gate insulation film 4.
Next, as shown in FIGS. 1b and 2, after the control gate 5, the gate insulation film 4, the floating gate 3, and the tunneling oxide 2 are selectively etched, leaving a predetermined width, and a silicon nitride film is deposited at a thickness of an order of 2,000 Å on the entire top surface, a side wall 6 is formed by blanket etch without using a separate mask.
Subsequently, a source 7 and a drain 8 are formed by injecting impurity ions into the semiconductor substrate 1.
When a positive voltage of certain conditions for programming of data in the flash memory having the structure as described above is applied to the gate, the hot electrons are injected into the floating gate as they move through a channel formed in the semiconductor substrate 1 under the tunneling oxide 2 and are accelerated by an electric field.
At this time, just as the injection of the hot electrons into the floating gate is shown by an arrow in FIG. 1b, the hot electrons are injected into not the entire surface of the floating gate but a point close to a drain 8, which shows the greatest potential difference, so called “pinch-off point”.
Similarly, when a negative voltage of certain conditions for erasure of data is applied to the gate, the electrons stored in the floating gate are injected into a source 7 by a potential difference.
At this time, as shown by the arrow in FIG. 1b, the electrons are injected into not the entire surface of the tunneling oxide but a point close to the source 7, which shows the greatest potential difference.
Therefore, in the above-described conventional flash memory, a whole capacitance is reduced by the tunneling oxide in an unnecessary portion where the injection of electrons does not occurs.
Since an application voltage has to be increased in order to compensate for the reduced capacitance, power consumption is increased. In addition, heat is generated due to the increase of the application voltage, which results in reduction of life of devices.